1. Field of the Invention
This invention relates to computers and, more particularly, to a method and apparatus for emulating the operation of a floating point stack utilizing processor registers.
2. History of the Prior Art
Many computers utilize a separate processing unit to accomplish mathematic operations. Historically, this separate unit has utilized a plurality of registers to operate on numbers in floating point format. At least one family of processors, the Intel X86 processors, utilizes a memory stack to accomplish floating point operations. The memory stack typically includes a limited number of sequential memory positions utilized as registers. The memory positions are filled in sequence as values are added to the stack and emptied in the opposite sequence as values are removed from the stack. The X86 floating point processor unit (FPU) keeps track of a moving register address called xe2x80x9ctop of stackxe2x80x9d at which values are entered and removed by incrementing or decrementing the top of stack address whenever an operand is entered or removed from the stack. The top of stack is also utilized as the position relative to which other positions are addressed for many of the operations of which the floating point unit is capable. Since the top-of-stack moves and other stack registers used in operations are addressed relative to top of stack, the addressing scheme utilized is often referred to as relative, implicit, or indirect addressing. Because of this type of addressing, floating point processors utilizing a stack arrangement (hereinafter referred to as a xe2x80x9cfloating point stackxe2x80x9d) accomplish floating point operations quite differently than do floating point processors using registers which are directly or explicitly addressed by register name.
Although the X86 processors are the most prevalent utilizing a floating point stack, there are other examples of such arrangements. Consequently, while this specification often uses the X86 designation as a shorthand in describing the invention, it should be understood that other examples of floating point stacks are intended to be included within the description. Moreover, the invention may be utilized in stack arrangements that are used for other than floating point operations.
A major difficulty with the original X86 relatively-addressed floating point stack is its limited ability to accomplish floating point operations rapidly. The original X86 floating point unit was designed with only eight memory positions functioning as registers. Eight positions are insufficient to always provide the various operands at the precise time they are needed to accomplish floating point operations. Eight positions allows little room for preprocessing or for storing results to be used in subsequent operations. Moreover, the floating point stack organization is such that it must implicitly update the top-of-stack after each operation on the stack; and prior art circuitry is designed to automatically accomplish this result.
Since the relatively-addressed floating point stack of the Intel X86 processors was utilized as the basis for a very large number of applications over a large number of years, any processor which is utilized to execute these applications must be able to carry out the operations of the X86 floating point stack.
Modern floating point processors utilize registers that are addressed directly and are not subject to the difficulties of floating point stacks. Modern floating point units have a relatively large number of individual registers so that preliminary computational operations may be carried out before their results are needed and results may be stored in the floating point unit for later use. Consequently, floating point units using directly addressed registers may function quite rapidly. However, it is quite difficult to utilize a floating point unit having directly-addressed registers to carry out floating point operations programmed to be carried out by a relatively-addressed floating point stack.
One modern processor is a very long instruction word (VLIW) processor designed to execute programs designed for other xe2x80x9ctarget processors.xe2x80x9d This VLIW processor typically receives its instructions in a form adapted to be executed by a target processor which has an entirely different instruction set than does the VLIW processor (the host processor). The VLIW processor dynamically translates a stream of target instructions into instructions of its own host instruction set and stores those translated host instructions so that they may be reexecuted without being translated again. This processor is described in detail in U. S. Pat. No. 6,031,992, entitled Combining Hardware And Software To Provide An Improved Microprocessor, Cmelik et al, issued Feb. 29, 2000, and assigned to the assignee of the present application.
This VLIW processor is often utilized to execute X86 programs. However, this processor utilizes a modern floating point unit with registers which are addressed directly.
It is desirable to provide a method and apparatus by which a modern floating point unit is able to execute floating point processes designed to be executed by a floating point stack more rapidly than can the floating point stack.
More particularly, it is desired to provide an improved addressing arrangement for enabling rapid execution of relatively-addressed stack instructions by an explicitly-addressed register array.
The present invention is realized by a floating point processor comprising a plurality of explicitly-addressable processor registers, an emulation register capable of storing a value used to logically rename the explicitly-addressable registers to emulate registers of a floating point stack, a computer-executable software process for calculating and changing a value in the emulation register to a value indicating a change in addresses of registers of a floating point stack when executing a floating point stack operation, and adder circuitry combining a register address and the value in the emulation register in response to the computer-executable process to rename the plurality of explicitly-addressable processor registers.
These and other features of the invention will be better understood by reference to the detailed description which follows taken together with the drawings in which like elements are referred to by like designations throughout the several views.